1. Field of the Invention
The present invention relates to a wiring board having electrode pads, conductor patterns connected to the electrode pads and an insulator layer embedded with the electrodes and the conductor patterns, and to a method of fabricating such a wiring board.
2. Description of the Related Art
Wiring boards having various shapes and structures have been proposed for use in mounting thereon electronic components such as semiconductor chips. Recently, there are increased demands to reduce the thickness and size of the wiring board mounted with the semiconductor chip, due to the reduced thickness and size of the semiconductor chip.
Known methods of forming thin wiring boards include the so-called build-up method, for example. The build-up method fabricates a multi-level (or multi-layer) wiring board by stacking on a core substrate build-up layers made of an epoxy resin material, for example, in order to form interlayer insulators for the wirings.
The core substrate is made of a prepeg material or the like, and supports the soft build-up layer prior to curing and suppresses warping caused by the curing of the build-up layer, during the fabrication process of the wiring board. However, the thickness of the core substrate, which forms the base for the wiring board, interferes with the further reduction in the thickness of the wiring board that is fabricated using the build-up method.
In order to further reduce the thickness of the wiring board that is fabricated using the build-up method, a method has been proposed to remove a support plate which supports the wiring board (or build-up layer) after forming the wiring board on the support plate by the build-up method, in a Japanese Laid-Open Patent Publication No. 2005-5742, for example.
FIG. 1 is a cross sectional view illustrating an example of a conventional wiring board. As illustrated in FIG. 1, an electrode pad 1 is formed on a support plate (not shown) which is removed by etching, for example, and an insulator layer 2 made of a resin material is formed to cover the periphery of the electrode pad 1. The electrode pad 1 is connected to a conductor pattern 3, such as a via plug. The electrode pad 1 may be formed by a stacked structure made up of an Au layer 1A and a Ni layer 1B, for example.
When forming the wiring board on the support plate using the build-up method, a surface 2A of the insulator layer 2 and a surface 10 of the electrode pad 1 are formed on the same plane. For this reason, delamination occurs at a boundary surface between a side surface of the electrode pad 1 and the insulator layer 2, at a portion indicated by A in FIG. 1.
As a countermeasure against the delamination described above, a structure has been proposed to form a wall portion that extends from an exposed surface of the electrode pad towards an opposite side from the exposed surface by modifying the shape of the electrode pad, in a Japanese Laid-Open Patent Publication No. 2005-244108, for example. However, when the shape of the electrode pad is complex as in the case of this proposed electrode pad structure, the number of processes required to form the electrode pad increases, to thereby increase the fabrication cost of the wiring board.
On the other hand, a structure in which the electrode pad is embedded in the insulator layer has been proposed in a Japanese Laid-Open Patent Publications No. 2004-64082 and No. 2003-229512, for example. However, according to this proposed structure, the delamination at the boundary surface between the electrode pad and the insulator layer cannot be suppressed satisfactorily, and it is difficult to prevent the reliability of the wiring board from deteriorating due to the delamination.